LOGIC FAMILIES - A GENERALIZED APPROACH

EDITOR: B. SOMANATHAN NAIR

The study of various logic families can be made simple by following certain basic rules regarding the structure of basic logic gates, which are discussed below. The main idea behind this is that any type of logic gates can be constructed using mechanical switches. These switches are then replaced with appropriate electronic devices which can act as switches to get the logic family bearing the name of that device. For example, when NMOS transistors are used to construct logic gates, then that family is called NMOS family. Let us now discuss a few basic logic gates constructed using mechanical switches.

1. AND GATE

Figure 1 shows the structure of an AND gate constructed using two series-connected mechanical switches A and B. To this combination of switches, we connect a load resistance R and a power supply +V as shown. There will be no current flow through the switches when either one of the switches or both the switches are open. The output voltage V_o will then be zero. This then represents logic 0. However, when both the switches are closed, current I will flow through load resistor R developing an output voltage V_o = IR = +V­ = logic 1. These actions represent the AND operation. Table 1 illustrates the working of the circuit. It may be noted that in these discussions, we choose an open switch to represent logic 0 and a closed switch to represent logic 1. 

From Table 1, we find that whenever A = 0 and B = 1, A = 1 and B = 0, or A = 0 = B, no current will flow through the circuit and hence there will not be any voltage drop across the load resistor R. So, under these three conditions, the output voltage V_o = 0 = logic 0. Now, when A = B = 1, both the switches are closed and, as stated above, I flows through R developing a voltage drop V across it. Thus, when both the switches are closed, output voltage V_o = +V = logic 1 (assuming that +V = logic 1). Now, verification of Table 1 shows that the circuit is acting as an AND gate.

2. NAND GATE

Figure 2 shows the structure of a NAND gate constructed using two series- connected mechanical switches A and B. There will be no current flow through the switches when either one of the switches or both the switches are open (i.e., A = 0 and B = 1, A = 1 and B = 0, or A = B = 0). The output voltage V_o will then be +V = logic 1. This is because when no current flows through R, there will be no potential drop across R and hence output potential V_o is the same as the supply voltage +V itself. But, when both the switches are closed (i.e., A  = B = 1) current I will flow through the circuit. In this condition, we find that the switches short circuit the output, making V_o = 0 = logic 0. This then represents the NAND operation. Table 2 illustrates the working of the circuit.

We now formulate a basic rule regarding the structures of the AND/NAND gates as given below.

BASIC RULE 1

Comparing the circuits shown in Figs. 1 and 2 indicate that a load located below the switches, connected in series and representing logic variables, will yield an AND gate, while a load located above those switches will yield a NAND gate.

We now use the above rule in constructing NMOS AND and NAND gates as shown in Figs 3 and 4, respectively. In Fig. 3, we have NMOS transistors T₁ and T₂ acting as electronic switches. T₃ is a depletion-mode transistor designed to act as the load resistor R. Since the load is below the switches, we find that the circuit will act as an AND gate.

In Fig. 4, the load resistance (transistor T₃) is located above the switching transistors T₁ and T₂. Then by Basic Rule 1, the circuit shown in Fig. 4 will perform NAND operation.

The generalized Basic Rule 1 can be used to construct AND and NAND gates using any active device (with appropriate modifications needed by the device used).

3. OR/NOR GATES

We now discuss the cases of OR and NOR gates using mechanical switches and their implementation using NMOS transistors.

BASIC RULE 2

A load located below the switches, connected in parallel and representing the logic variables, will yield an OR gate, while a load located above those switches will yield a NOR gate.

Figure 5 shows an OR gate constructed using two mechanical switches and Fig. 6 shows its implementation using NMOS transistors. For the OR gate, we find that I will not flow when both the switches are open (i.e., A = B = 0). The output voltage V_o will then be 0 V = logic 0. However, I will flow through the circuit when one or both the switches are closed (i.e., A = 0 and B = 1, A = 1 and B = 0, or A  = B = 1). Then the output will be +V = logic 1.

Similarly, Fig. 7 shows a NOR gate constructed using two parallel mechanical switches and Fig. 8 shows its implementation using NMOS transistors. In this case, we find that current will flow when A = 0 and B = 1, A = 1 and B = 0, or A = B = 1). Then the output will be 0 V = logic 0, since one or both of the switches short circuit the output. However, when both the switches are open, no current will flow through the circuit, and therefore the output is at +V = logic 1.

The relevant truth tables are shown in Tables 3 and 4, respectively.

4. NOT (INVERTER) GATE

Figure 9 shows a NOT gate constructed using a mechanical switch and Fig. 10 shows its implementation using NMOS transistors. Table 5 shows the truth table of NOT gate. When the input A = 0, the circuit is open and hence output is at +V = logic 1. But, if the input is at logic 1 (i.e., +V), the switch is closed and current flows through the load; the switch then short circuits the output making it logic 0. 

BASIC RULE 3

NOT gates can be obtained by connecting the load located above the switch representing the logic variable (as in the case of NOR and NAND gates).

5. CONCLUSION

The three basic rules given above cam be used to construct any type logic gates using any active devices. Even though this is a general statement, it is easy to implement these gates using NMOS or PMOS transistors since they are almost perfect switches. Further, the implantation can be done as an all-transistor affair since MOS transistors can also be used as resistors and capacitors.  

In the next blog, we shall discuss the implementation of logic gates using CMOS technology.