RC-COUPLED JFET COMMON SOURCE AMPLIFIER – A STEP-BY-STEP SYSTEMATIC APPROACH TO PRACTICAL DESIGN

EDITOR: B. SOMANATHAN NAIR

           In this blog, we present the step-by-step design of an RC-coupled junction field-effect transistor voltage amplifier in the common-source mode.  Figure 1 shows the structure of the specified amplifier and Fig. 2 shows the voltage distributions across various terminals of the FET.

            In Fig. 1, drain resistor R_D is used for fixing the Q-point in the drain circuit. We know that for proper operation, the gate of a JFET must be reverse-biased with respect to its source. For this, we employ a technique known as self-bias.

         In the self-bias technique, the drain current flowing through source resistance R_S develops a potential drop V_RS across it, with polarity as shown in Fig. 1. In this condition, we find that the source is more positive with respect to the ground. Since there is no current through the gate of the JFET, the input impedance of a JFET is very high and hence we connect a large resistance R_G (typically, 1 MΩ) between the gate and the ground. As stated, since there is no current through the gate, there will be no current through R_G, and hence there is no voltage drop across it. This then makes the gate also to be at ground potential. Thus we find that the gate is reverse-biased with respect to the source. Since this bias is developed by the circuit on its own, it is called self-bias.            

      The source resistance R_S is bypassed by C_S to reduce the effect of negative feedback in the amplifier and thus increase the gain obtainable. As in the case of the BJT amplifier, in this case also, C_C1 and C_C2 are the coupling capacitors, and R’_L and C’_L are the load resistance and capacitance, respectively.

1.  SPECIFICATIONS

·         Voltage gain                      :           10

·         Output swing                     :           5 V (peak)

·         Bandwidth                         :           100 kHz

NOTE:  The design of FET amplifiers is based on the availability of suitable FETs.  In our designs, we shall be using BFW 10 or BFW 11, since they are the most commonly available types in the market. As we have only two JFETs at our disposal, a severe limitation exists in prescribing our specifications. For example, the amplification factors of BFW 10 and 11 lie in the range of 10 to 15 only. Hence it is very difficult to get high gains using these transistors. Also, the current swing will be limited to a maximum of 10 mA only.

2.    DESIGN STEPS

Step 1: Fixing the Q-Point

In JFETs, the Q-point is fixed at the middle point of the transfer curve, shown in Fig. 3. For BFW 10 and 11, the cut-off voltage V_P −4 V. For the maximum symmetrical swing, we select the quiescent gate-source voltage V_GSQ according to the equation

                                                                V_GSQ = V_P/2                         (1)

Substituting values, we get

                                                            V_GSQ = −4/2 = −2 V.

NOTE 1: In some situations, the amplifier designed using V_P = −2 V may not work properly. In such cases, we have to plot the transfer curve (V_GS-I_D) experimentally, and find the value of V_P.

Step 2: Determination of Drain Current I_D

To fix V_DS at −2 V, we have to compute the value of the source resistance R_S. For this, the magnitude of the drain current I_D is required. I_D is determined from the empirical relation

                                               

                                                            I_DQ = I_DSS[1‒(V_GSQ/V_P)]²    (2)

where I_DQ is the drain current at the specified V_GS, and I_DSS is the saturation drain current or drain current for V_GS = 0 V (obtainable from data-manuals). As in the case of BJT amplifiers, in our designs using FETs also, we will use the minimum values of parameters such as I_DSS. For BFW10, I_DSSmin = 4 mA. Hence we get

         I_DQ = 4(1 – 2/4)² ´10⁻³ = 2 mA

Step 3: Design of R_S

From Fig. 3, which shows the transfer curve and load lines of the JFET, we have

                                                                                    

                                                            R_S=V_RS/I_DQ = V_GSQ/I_DQ                (3)

where V_RS is the voltage across R_S. Substituting values, we get R_S = 2/1´10⁻³ = 2.2 kΩ.

Step 4: Fixing V_DD

For symmetrical swing (see Fig. 2), we must have V_DS = V_RD, where V_DS is the drain-source voltage and V_RD is the voltage drop across R_D. Also

                                                            V_DD = V_DS+V_RD+V_RS            (4)

where V_DD is the drain supply voltage. We then get

                                                                             

                           V_RD = (V_DD  ‒V_RS)/2            (5)

In our problem, we require a voltage swing of 5 V. Therefore, V_DS = V_RD = 5 V. Hence we can now fix the supply voltage at

                                                                      V_DD = 2V_DS+V_RS          (6)

Substituting values, we have

              V_DD = 10 + 2 = 12 V

Step 5: Design of R_D

The drain resistance R_D is obtained as

                                                            R_D = V_RS/I_DQ                        (7)                                                                     

Substituting values, we get R_D = 5/(l ´ 10⁻³) = 5 kΩ, choose standard 5.6 kΩ.

Step 6(i): Design of Gate Resistance R_G

The purpose of R_G is to connect the gate to the earth so that the required bias appears between the gate and source terminals. Since the gate is reverse-biased, we assume that the current flowing through R_G is negligible. Therefore, we select R_G to be very high, so that it will not load the high input impedance of FETs. Usually, JFETs have typical input impedance of about a few MΩ. Hence R_G can be chosen to be anywhere between 1 MW to 10 MW. A very convenient value that can be chosen is R_G = 1 MW.

NOTE 2: Sometimes, R_G may be replaced by a voltage-divider biasing consisting of resistors R₁ and R₂, as shown in Fig. 4. In such a situation, we adopt the following method for designing R₁ and R₂. 

Step 6(ii): Design of voltage-divider biasing resistors R₁ and R₂

Assuming V_RS > V_GS, we have the gate-to-source voltage

                                                              V_GS = V_RS – V_GG               (8)

Where V_GG is the gate-supply voltage, given by

V_GG = V_DD R₁/ R₁+ R₂               (9)

                                                               

We use the same numerical values used in the previous design. Thus, we have V_OP = 8 V, I_DSS = 4 mA, V_P= –4 V, and V_GS= −2 V. With V_GS = −2V, we must have V_RS = −4 V, so that

                                                           V_GG = V_RS – V_GS = −2 V       (10)

            The requirement here is that V_RS >V_GS.  Therefore, any higher value may be appropriate for V_RS.  However, a value of 2 V will be quite convenient from the point of view of designing the biasing resistors R₁ and R₂. Notice that the higher the magnitude of V_RS, the higher the drain-supply voltage required. Now, drain-supply voltage

                                                            V_DD = 2V_RD + V_RS              (11)

Substituting values, we have

V_DD =16 + 4 = 20 V.

Then  

R₁/ (R₁+ R₂) = V_GG /V_DD = ‒2/‒20 =  1/10  (12)

      We require one more condition to determine the values of R₁ and R₂. This can be obtained by considering the fact that R₁ and R₂ come in parallel to the input impedance of the FET. Since the input impedance of the JFET is very high (on the order of a few MW), we must choose R₁ and R₂ such that their effective (parallel) value will be the same as that of the input impedance. This will prevent the loading of the input by R₁ and R₂. Thus, we choose R₁ = 1 MW and R₂ = 10 MW.

Step 8: Design of Bypass Capacitor

Bypass capacitor C_S may be designed by using the expression

                                                                        

                                                            X_CS = 1/2πf_LC_S              (13)

where f_L is the lowest operating frequency of 30 Hz. Substituting values, we get

C_S   = 1/2πx30x2.2x10³ = 2.4 μF

Choose a higher value of C_S = 5 mF.

Step 9: Design of Coupling Capacitors CC Here also, we use the same type of design equation as was used in the BJT-amplifier design. Thus                                                                                                                                                                                                                   CC = 1/2πfLRG                (14) Substituting for fL = 30 Hz and RG = 1 MW yields CC = 0.005 mF, choose 0.01 mF. The completely designed circuit is shown in Fig. 5.             As R’L and C’L are parameters of external load, we can not design them. However, we can simulate them in the lab for conducting experiments. For simulation, we may use a 100-kΩ resistance in parallel to a 1-nF capacitor as the load.