CMOS TRANSISTOR LOGIC FAMILY

EDITOR: B. SOMANATHAN NAIR

1. INTRODUCTION

The complementary-symmetry metal-oxide semiconductor (CMOS) transistor logic gates are manufactured using a combination of  NMOS  and  PMOS  FETs in their complementing modes, For example, a CMOS NAND gate is constructed by connecting an NMOS NAND gate to a PMOS NOR gate in a fashion such that the PNOR becomes the load of the NNAND and vice versa. This means that the load of the NAND gate is the NOR gate and the load of the NOR gate is the NAND gate.

        In this context, it may be noted that the NMOS FETs act as positive-logic devices and the PMOS FETs act as negative-logic devices. For example, in the case of the CMOS NAND structure, the NMOS NAND performs the positive-logic function and the PMOS NOR performs the negative-logic function. Also, from De Morgan’s laws, we know that an NMOS NAND gate is equivalent to a PMOS NOR gate. Then, by combining the complementary structures of the NMOS and PMOS transistors in appropriate fashion, we can construct any desired CMOS logic gate. The following basic rule helps in this process.

2.  BASIC RULE FOR CMOS STRUCTURES

For any CMOS structure, the basic gate must be constructed using NMOS transistors. The PMOS structure, which is connected on top of the NMOS structure, must be the complementary of the NMOS structure (the word “top” is used here with reference to the circuit diagrams shown only; in actual construction of the circuit, there is no top or bottom).

           As an example, as stated earlier, CMOS NAND has NMOS NAND as the basic gate. PMOS NOR is then connected on top of this as its complementary circuit. Similarly, in the case of CMOS NOR, the basic gate is NMOS NOR, above which we have PMOS NAND as its complementary. This rule follows in all CMOS structures..

            It may further be noted that we can simulate NMOS and PMOS gates by ON and OFF switches. These models are also discussed below.

3. CMOS NOT (INVERTER) GATE

A CMOS inverter can be constructed by connecting a PMOS transistor as the load resistance of an NMOS transistor, as shown in Fig. 1. Figure 2 shows the inverter constructed using mechanical switches.

            Referring to Fig. 1, when input A = 0, the NMOS is OFF, but the PMOS conducts and the output is +V (≡ logic 1). When A = +V (≡ logic 1), the NMOS conducts but the PMOS is OFF. Hence the output Y= 0 volt (≡ logic 0), as it is shorted by T₁. Thus we find that the circuit shown in Fig. 1 performs the NOT operation.

      The circuit constructed using switches, shown in Fig. 2, also performs similarly. When A = 0 (open switch), Switch 2, which is ON, conducts and output Y = +V= logic 1. But, when A  = +V (≡ logic 1), Switch 1 turns ON and acts as a dead short between the output terminals as a result of which the output is 0 (≡ logic 0). These operations indicate that the circuit shown in Fig. 2 performs NOT operation. We notice that that Switch 1 represents the NMOS transistor, and Switch 2 represents the PMOS transistor.

4. CMOS NAND GATE

As stated earlier, CMOS NAND is a combination of an NMOS NAND gate with a PMOS NOR gate as its load or vice versa. The circuit of the CMOS NAND is shown in Fig. 3. As shown, both the input terminals A of transistors T_1N and T_1P are shorted together to form the single input terminal A. Similarly, both the input terminals B of T_2N and T_2P are shorted to form the single input B. Let A = B = 0. In this case, both the PMOS transistors conduct and the NMOS transistors remain OFF. So, output Y = +V_DD ≡ logic 1. Also, when one of the inputs (A or B) is 0 and the other (B or A) is 1, the same situation prevails. However, if both A = B = 1, then the PMOS FETs remain OFF and the NMOS FETs conduct short circuiting the output. This makes the output to fall to 0 V (I.e., to logic 0). This is NAND operation.

Figure 4 shows the NAND constructed using switches. Here, the bottom block of series-connected OFF switches represent the NMOS NAND and the top block of parallel-connected ON switches represent the PMOS NOR.

5. CMOS NOR GATE

A CMOS NOR gate can be constructed by connecting an NMOS NOR gate to its complementary PMOS NAND gate as shown in Fig. 5. The working of CMOS NOR is as follows. When input A = B = 0, both T_1N and T_2N remain OFF, but T_1P and T_2P turn ON. Thus +V_DD reaches the output through the conducting transistors T_1P and T_2P, and we have Y = +V_DD ≡ logic 1. But, when A = 0 and B = 1, T_1P and T_2N conduct, but T_2P and T_1N remain OFF. As T_2N is ON, Y = 0 volt ≡ logic 0. The same situation prevails when A = 1, and B = 0, as well as when A = B = 1. We find that Y = 0 under these conditions. These conditions suggest that the CMOS circuit shown in Fig. 4 performs the NOR function.

6. COMPLEX CMOS GATES

Circuit diagram of complex CMOS gates can be drawn by employing the same rule used for the drawing of the CMOS NAND and NOR gates: Draw the basic gate from the equation given using NMOS transistors; then on top of this gate, draw its complementary-function gate using PMOS transistors. To illustrate the idea further, let us consider the design of a CMOS gate which should yield the logic expression Y = [A(B+CD)]′.

      To develop the CMOS implementation of the given expression, we first develop the NMOS circuit diagram which produces the expression Y = [A(B+CD)]′. As shown in Fig. 6, the series combination of the NMOS transistors C and D produces the expression CD (actually, the output of the NAND is (CD)′. However, we neglect the negation for the moment; it will be introduced only in the final expression of output Y. Now, to get the term B + CD, we connect the input B in parallel with the series combination of C and D. Now to this combination, we add transistor A in series, as shown in Fig. 6 to yield the desired expression Y = [A(B+CD)]′. Notice that the final expression contains the negation sign in it. This is due to the inversion of the function by the transistors involved.

       Next, we draw the complementary circuit using PMOS transistors. For this, we find that the complementary circuit of the NAND structure CD is C+D. The term (B+CD) has its complementary function B(C+D). Finally, the negated complement of A(B+CD) is [A+B(C+D)]′. This is implemented using PMOS transistors, as shown in Fig. 7. 

       Finally, the PMOS and NMOS structures are now combined as shown in Fig. 8 to yield the desired CMOS gate, which will produce the logic expression Y = [A(B+CD)]′.

       Thus, as stated above, to construct the CMOS gate of a given logic function, we first implement it using NMOS gates and then on top of this NMOS structure, implement  its complement using PMOS gates.