Saturday, 12 May 2018

DESIGN OF ASTABLE MULTIVIBRATOR USING BJTs


EDITOR: B. SOMANATHAN NAR

           
I. DESIGN FOR SYMMETRICAL WAVEFORMS

1. SPECIFICATIONS

·         Free-running Frequency                :           5 kHz
·         Output-voltage Swing                    :            10 V
·         Rise time                                        :            10 ms
·         Duty cycle                                       :            50%

2. DESIGN PROCEDURE
The first step in our design of the astable multi begins with the design of a two-stage Standard Amplifier. We design the amplifiers such that their Q-points will be in the middle of their respective active regions. As the overall gain of the two stages is far higher than unity (approximately, more than 104 for a two-stage amplifier using BC 107 transistors), the back-to-back connections convert the two-stage amplifier into an oscillator that will produce square waves. The design described here is contradictory to the usual design of the astable multi in the saturation and cut-off modes. The unique feature of the design in the active region is that it will ensure sure oscillation of the circuit as it is that of a standard positive-feedback oscillator design.
For active region operation, we must have voltage divider biasing resistors and emitter resistors, a common feature of the standard RC-coupled amplifier. However, since the gain is very large the transistors will be operating in their saturation and cut-off modes, which are stable states. Therefore, we can remove both the emitter resistors from the circuit, as it is used for temperature stability. Based on the same argument, we may also replace biasing resistors R1 and R2 with a single resistor RB. Thus, the structure of the astable multi becomes highly simplified. The astable multi to be designed is in shown in Fig. 1.





3. DESIGN STEPS

Step 1: Fixing VCC
From Fig. 1, we find

                                                            VOP = VCC VCESAT = VCC      (1)

where VCESAT = 0.2 V only and hence neglected. In our current design problem, we require VOP = 10 V. Therefore we fix

            VCC = 10 V                                                  

Step 2: Selection of Transistor
As in the design of the RC-coupled Standard Amplifier (for design of the standard amplifier, see the earlier blog on RC-coupled amplifier), transistors selected must be capable of handling 2ICMAX and 2VCEMAX where ICMAX is the maximum collector current, and VCEMAX is the maximum collector-to-emitter voltage. Select BC 107 which meets these specifications.

Step 3: Selection of IC
Select any suitable value of IC, say, between 1 mA and 10 mA, as this is a low-power design. In our problem, we choose

IC = 1 mA


Step 4: Design of RC
Since this a Standard-Amplifier design, for operation in the active region, from Fig. 1,

                                                            VRC = VCEQ = VCC/2    (2)

where VRC is the voltage across RC and VCEQ is the quiescent (steady-state) voltage across the collector and emitter of the transistor. Now, if IC is the current through RC, then we find
                                                           
                                                    RC = VRC/IC = VCC/2IC    (3)
                                                                                                                                                      
Substituting values, we get
  
                                                    RC = 10 V/2x1 mA = 5 kΩ

Choose the nearest standard resistor of 4.7 kΩ as RC.
   
Step 5: Design of RB
From Fig. 1, we observe that the voltage drop across RB

                                   VRB = VCCVBEQ                                                          

where VBEQ  is the base-emitter quiescent voltage (= 0.65 V). Also

IBQ = IC/βmin

And
 RB = VRB/BQ = (VCCVBEQ) βmin/IC (5)


Substituting values, we get

        RB = (10−0.65) V/1 mA = 1 MΩ

Step 6: Design of C
The specification demands 50% duty cycle. Duty cycle is defined as
                                                D = TA/(TA + T) = TA/To (6)

where TA and TB are the two half-cycles of oscillation and To = 1/fo. The specification of 50% duty cycle indicates that the waveform is symmetrical. Hence, we use the expression for the free-running frequency of the multivibrator

                                                            fo = 1/1.38RBC  (7)

for symmetrical operation. Using Eq. (7), we get

C = 1/1.38RBfo   (8)
                                                                                                                            
Substituting values yields

C = 1/1.38x106x5x103 = 0.15 nF
                                                          
Step 10: Design for the Desired Rise Time
The rise time is given by
                                                           
                                                            tr = 1.6/foβmin  (9)

From Eq. (9), we find that to get a shorter rise time, the transistor selected must have a large β. Substituting values, we get

tr = 1.6/5x103 x100 = 3.2 μ


This is less than the required value of 10 ms. Hence the selection of BC 107 is justified. The fully designed circuit is shown in Fig. 2.





II. DESIGN FOR UNSYMMETRICAL WAVEFORMS

1. INTRODUCTION
In Section I, we discussed the design of astable multivibrator that produces symmetrical square waveforms. In such waveforms, the duty cycle is 50%, i.e., the two half-cycles are of equal duration. Now we undertake the design of an astable multivibrator that produces unsymmetrical waveforms (i.e., waveforms having unequal half-cycles or different duty cycles). Equation (6) states that

                                                            D = TA/(TA + T) = TA/To
From which we find
 
                                                             TA = DTo = D/fo                           (10)
                                                               
                                                TB = ToTA = ToDTo = (1 – D)/fo        (11)

We know that for a free-running multivibrator

                            TA = 0.69RBC1  (12)
                             TB = 0.69RBC2    (13)

where we keep RB constant for biasing reasons and choose two different values for capacitors. From Eqs. (12) and (13), we find the values of the capacitors

C1 = TA/0.69R = D/fox0.69RB   (14)
                                        C2 = TB/0.69RB= (1–D)/fox0.69RB  (15)
                         
Using these design equations, we can determine the values of the capacitors that produce the waveforms having desired duty cycle.
                                                                                 
2. SPECIFICATIONS

·         Free-running Frequency                :           5 kHz
·         Output-voltage Swing                    :            10 V
·         Duty cycle                                      :            25%

3. DESIGN PROCEDURE 
Step 1: Choice of C1
Choosing RB = 1 M, fo = 5 kHz, and D = 0.25 and substituting in Eq. (14), we get
            
C1 = D/fox0.69RB = 0.25/0.69x106x5x103 = 72 pF

Step 2: Choice of C2
Similarly, from Eq. (15), substituting values

C2 = (1–D)/fox0.69RB = (1–0.25)/0.69x106x5x103 = 216 pF

The fully designed circuit for unsymmetrical waveforms is shown in Fig. 3.

NOTE: In the design, we change only C’s, and do not touch RB’s at all. This is because, if RB’s are changed, the biasing will be affected and the circuit may not oscillate at all.





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