RC-COUPLED COMMON-EMITTER AMPLIFIER - A SYSTEMATIC APPROACH TO DESIGN

EDITOR: B. SOMANATHAN NAIR

In electronic circuit theory books, electronic circuit designs are not given in a proper manner. Hence a student finds it difficult to design and construct a circuit so that he/she can test it for proper functioning. A proper engineering design requires step-by-step procedure so that the final design can be implemented directly without any confusion. In this article, we give a standard procedure for the design of a common-emitter voltage amplifier in the class-A mode of operation.

It may be noted that the designs given here are for circuits using discrete devices which are part of first or second year curriculum in electronics. 

1. GIVEN SPECIFICATIONS

An engineering design is done based on the requirements of a given practical problem. These requirements are called specifications. Our first task is therefore to design a single-stage RC-coupled common-emitter class-A voltage amplifier to meet the following specifications:

·         Voltage gain                 :          100 (minimum)

·         Voltage swing               :          9 V (peak-to-peak)

·         Current swing               :          1 mA (peak)

·         Bandwidth                    :          100 kHz (maximum)

2. DC AND AC LOAD LINES

An RC-coupled class-A voltage amplifier can be designed with the help of the DC and ac load lines. Figure 1 shows theoretical DC and ac load lines and Fig. 2 shows them using practical numerical values.  DC load line is the straight line connecting the supply voltage V_CC and the maximum DC current I_CMAX. V_CC also represents the maximum value of collector-to-emitter DC voltage V_CEMAX, when the DC collector I_C = 0. Similarly, the maximum value of collector current I_CMAX occurs when V_CE = 0. From Fig. 1, we find

I_CMAX = V_CC /(R_C +R_E)

In the above equation, let V_CC = 10 V, R_C = 4.5 kΩ, and R_E = 1 kΩ, then

            I_CMAX = 10 V /5.5 kΩ = 1.82 mA

Now we draw the DC load line in this case by joining the V_CC (=10-V) point on the voltage (x) axis and the I_CMAX (1.82-mA) point on the current (y) axis, as shown in Fig. 2. It may be noted that in computing I_CMAX, we have included emitter resistor R_E as it forms part of the DC collector-emitter path.

            To draw the ac load line, we have to compute the maximum value of ac collector-emitter voltage V_cemax and the maximum value of ac collector current I_cmax. Since emitter resistor R_E is usually bypassed with capacitor C_E, it can be neglected from computations. Similarly, since the effect of R_E does not come under signaling (or, ac) condition, the DC voltage drop across it can be neglected. Therefore the effective peak-to-peak value of the collector-emitter voltage V_ce(p-p) under signaling conditions is given by

V_ce(p-p) = 2V_cemax = V_CC ‒ V_RE

In our example, if V_CC = 10 V, and V_RE = 1 V, then

V_cemax = (10 ‒1)/2 = 4.5 V

This represents the point of the ac load line on the voltage axis. To find the current point of the ac load line, we compute the maximum value of ac current using the expression

I_cmax  =  V_ce(p-p) /R_C = 2V_cemax / R_C

In our example, since V_cemax = 4.5 V and R_C = 4.5 kΩ, we obtain

I_cmax  = 4.5 V /4.5 kΩ = 1 mA

By joining the 9-V point on the x axis and the 2-mA point on the y axis, we draw the ac load line, as shown in Fig. 2.

            We have seen that V_cemax is the maximum possible value of the swing in the signal output voltage. For symmetrical swing in the output voltage, therefore, we must have

V_cemax = V_CEQ = V_ce(p-p)/2

where V_CEQ is the steady-state, quiescent, or DC collector-to-emitter voltage. It is also the voltage across the collector and the emitter of the transistor immediately after the circuit has been switched on and with no input signal being applied. I_CQ is the DC collector current corresponding to V_CEQ.

             It is interesting to note that the ac and the DC load lines cross each other at the V_CEQ-I_CQ point, as shown in Fig. 1. It can be seen that the amplified signal voltage V_ce varies symmetrically with respect to V_CEQ to produce the maximum output voltage swing V_cemax, as shown. Similarly, collector signal current I_c varies symmetrically about I_CQ to produce the maximum output current swing I_cmax, as shown. We thus find that choosing the correct operating (Q) point V_CEQ-I_CQ helps in achieving the maximum swing in the output voltage and current. Thus it is clear that using the load lines to design an amplifier is an optimum procedure.

Figure 3 shows the voltage drops across various terminals of the BJT and Fig. 4 shows the numerical values of the voltage drops used in the design example.

We now make use of Figs. 2 and 4 in our design example, which is described below.

3. DESIGN PROCEDURE

Step 1: Fixing V_CC

As explained above, from Fig. 3, we have

                                                        V_CC =V_RC + V_CE + V_RE                (1)

where V_RC is the voltage across collector resistor R_C, V_CE is the voltage across the collector and the emitter, and V_RE is the voltage across emitter resistor R_E. For maximum symmetrical swing, from load-line analysis, we find the requirement

                                                               V_RC = V_CE                              (2)

And, for temperature stability, we take (as a rule-of-thumb)

                                                            V_RE = 0.1 V_CC                                      (3)

It may be noted that the larger the value of V_RE, the better it is for temperature stability. However, a larger value of V_RE means a lower output voltage swing. To compromise between the two contradictory requirements, we choose the condition given in Eq. (3). Now, using Eqs. (1), (2), and (3), we get the peak-to-peak output voltage V_ce(p-p) as

                                                     V_ce(p-p) = 2V_RC = 2V_CE = 0.9V_CC          (4)

From this equation, we get the supply voltage

                                                    V_CC = V_ce(p-p)/0.9 = 2V_cemax/0.9             (5)

where V_cemax (maximum value of the output voltage) = V_ce(p-p)/2. In the given problem, V_cepp = 9 V. Therefore we fix the supply voltage

V_CC = 9/0.9 = 10 V

Step 2: Fixing I_C

The collector current I_C is fixed according to the current swing required. From Fig. 3, I_C=I_CQ=I_{c max}, where I_CQ = value of collector current under quiescent, steady-state, or zero-signal condition. It can be seen from Fig. 3 that I_C (=I_cmax) also represents the peak value of the ac collector current under signaling condition. Hence I_C is fixed at this value. In our problem, the desired current swing is 1 mA. Therefore, we choose

I_CQ = 1 mA

Step 3: Selection of the Transistor

Selection of a suitable bipolar junction transistor is based on the following facts:

·      V_CEMAX : This is the maximum voltage across the collector and emitter terminals, which the transistor can withstand without breakdown. Assuming V_CEMAX = V_CC (when I_C = 0), we may choose a transistor whose V_CEMAX is at least 2V_CC. In this case, we have chosen a factor-of-safety of 2.

·      I_CPP : This is the peak (maximum) value of collector current that can safely flow through the transistor at any instant. This is equal to 2I_CMAX. The transistor must be able to withstand this also. Usually, for safety, we choose a transistor that can withstand at least twice this current.

·      A_v : This represents the voltage gain of the transistor = bR_L/R_i, where, b or h_FE is the current amplification factor of the transistor, R_L is the load resistance, and R_i is the input impedance of the amplifier. Assuming that R_L= R_i (usually, R_L >> R_i), we find that A_v = b. This expression puts us in some difficulty. We know that b  varies widely even for the same type of transistor. For example b of BC 107 varies roughly from 125 to 500. Which value of b is to be chosen for designing the amplifier?

                   To find a solution to the above question, consider the value of b of BC 107 itself. As stated above, this varies from125 to 500. This means that all BC 107 transistors will have a             minimum guaranteed value of b (hereafter referred to as b_m­in) equal to 125. Current gain b of values greater than this (up to 500) can surely exist; but the manufacturer does not guarantee any value other than the minimum value of 125. This forces us to design the amplifier by using the minimum value of b. In fact, in all our future designs, we shall be using only the minimum value of a parameter, if that parameter has a wide range of variation in its value.

·         Voltage gain given by the expression A_v=βR­_L/R­_I is only approximate because it is dependent on the highly variable parameters of b, R_i, and R_L. Assuming R_L= R_i, it yields a gain lying between b_min and b_max. To get the required gain to the exact value desired, we must use negative feedback techniques. Taking into account of the above facts, from the data manual, we choose

BC 107

 which has I_CMAX=10 mA, V_{CE MAX}= 45 V, and b_min=125, as the amplifier device.

Step 4: Design of R_C

Collector resistor R_C may be designed by using the expression

                                                 R_C = (V_CC ‒ V_RE)/2I_C    (6)

Combining the equations given above, we get

                                                   R_C = 0.9V_CC/2I_C           (7)

Substituting,

                       

  R_C = 0.45´ 10/10⁻³ = 4.5 kW

Resistors have finite power rating beyond which, if operated, they are sure to fail. To avoid this, we must also specify the power rating of resistors. Power rating P of a resistor

                                                        P = 2(I_max)²R            (8)                    

where I_max = maximum current through the resistor. The factor 2 is used as a factor-of-safety. To find the power rating of collector resistor R_C, we use the modified equation

                                                        P = 2(2I_CQ)²R_C            (9)                 

  where 2I_CQ is the maximum current that can flow through the collector when V_CE = 0 V. The maximum value of collector current is also the collector-current swing. So we use I_max= 2 mA. Substituting values,

P = (2 × 10⁻³)² ´ 4.7 ´ 10³ = 0.0376 W

The nearest value of standard carbon resistor (with ± 10% tolerance) is 4.7 kW with (1/8)-W rating. Therefore, we select

R_C = 4.7 kW / 0.125 W

Step 5: Design of R_E

As stated earlier, to choose R_E, the following conditions must be satisfied:

i.   R_E should be as high as possible so that Q point is stabilized. It can be proved from stability analysis that the collector current is stabilized against variations in I_CO and V_BE, if R_E is high. The higher the value of R_E the better the stabilization we get.

 ii. However, if R_E is high, the swing in the output voltage will be reduced.

Conditions (i) and (ii) are contradictory to each other. In order to compromise between these two conflicting requirements, we choose, as a rule-of-thumb

                                                            V_RE = 0.1 V_CC             (10)

            In our design problem, V_RE = 0.1 ´ 10 = 1.0 V. Since R_E = V_RE/I_C, we find R_E = 1/1´l0⁻³ =1 kW. We select

R_E = 1 kW / 0.125 W

Step 6: Design of the Biasing Network consisting of Resistors R₁ and R₂

The bias network consists of resistors R₁ and R₂. The design of these resistors is based on the stability analysis of the amplifier since the stability of the operating point is mainly dependent on these resistors. From stability analysis, we have

                                   

                                                             b_min/10 = R_B/R_E            (11)

where

                       

                                                               R_B = R₁R₂ /(R₁ + R₂)    (12)

Also, from Fig. 4, we get

V_R1 = V_CC R₁ /(R₁ + R₂)    (13)

But

                  V_R1=V_BEQ+V_RE                 (14)

where V_BEQ is the quiescent or steady-state base-emitter voltage of the transistor. This is the operating or Q-point of the transistor. By steady-state operation, we mean the operation of the amplifier when no signal is present. The base-emitter active-region voltage of silicon transistors usually vary exponentially from 0.5 V to 0.8 V. In such a case, V_BEQ is usually taken as 0.7 V. However, with Indian transistors, the authors have found that V_BEQ has the best value between 0.6 V to 0.65 V. Choosing 0.65 V, we haveV_R1= 0.65+1.0 = 1.65 V. Solving

                        R₁ = R_B/(1‒a)                  (15)

and

           R₁ = R_B/a                            (16)

                                                                                                

where

                                                               a =    V_R1 / V­_CC                      (17)               

Substituting values, we have

R₁ = 15 kW and R₂ = 82 kW.

The above values are obtained by considering that b_min of BC 107 is 125. However, it is found that b_min of the Indian-made BC 107 transistor is only around 100 in majority of the cases. Therefore, recalculating for R₁ and R₂ yields the values of R₁=12 kW (1/8 W), and R₂ = 68 kW (1/8 W).

Step 7: Design of Bypass Capacitor C_E

C_E is used to bypass AC signal across R_E. For designing this, we use the expression

                                                                    f_L = β/2πR₁C_E­                (18)

               

where f_L (lower half-power frequency) = 30 Hz for AF amplifiers. Substituting values, we find

                                                                    C_E = 50 mF/10 V

Step 8: Design of Coupling Capacitors C_C1 and C_C2

C_C1 and C_C2 are designed using the expression

  

                                                                      f_L = β/2πR₁C_C                      (19)

                                                                 

Substituting values, we get             

                                                             C_C1 = C_C2 = 5.6 mF

    

   Choose a higher value, say, 10 mF/10 V

Step 9: Design for a Bandwidth of 100 kHz

The bandwidth of an amplifier is determined by the high-frequency response of the amplifier. This, in turn, is determined by the load capacitance C'_L. If f_H denotes the upper half-power frequency, then

                                                            f_H = 1/2πR_LC_L                        (20)

Given f_H = 100 kHz, and assuming R’_L = R_C we get

C’_L= 0.4 nF

The completely designed am plifier is shown in Fig. 5. This amplifier is called as the Standard Amplifier in this text.

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